1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device having a fuse circuit.
2. Description of the Related Art
As a semiconductor integrated circuit device which has a fuse circuit, a semiconductor memory is well known. The semiconductor memory has a memory cell array with memory cells which are memory elements arranged in a matrix. The semiconductor memory has a spare memory cell (redundant cell) in addition to a regular memory cell (normal cell). When the normal cell fails, the failed normal cell is replaced with the redundant cell. This is a so-called redundancy technique.
For example, in order to identify a failed normal cell, the position thereof, that is, a failure address must be identified in the redundancy technique. In the event that the failure address is unknown, it is unable to be replaced with the redundant cell. In order to identify the failure address, the semiconductor memory has a fuse circuit in addition to the memory cell array. The failure address is stored in the fuse circuit. The memory element mounted in the fuse circuit is in general a fuse. The fuse stores “0” or “1” data depending on whether or not the current route is physically cut. The fuse is one of nonvolatile memory elements. Hereinafter, the fuse is called a fuse cell in the present specification.
Fuse cells are integrated in the fuse circuit, but a structure of the fuse cell differs from a structure of the memory cell. Consequently, a fuse cell manufacturing process differs from a memory cell manufacturing process and a fuse cell forming step is separately required. Therefore, in a nonvolatile semiconductor memory of semiconductor memories, there is an example in which a fuse cell is replaced with a nonvolatile memory cell. The example is U.S. Pat. No. 6,052,313. As described in U.S. Pat. No. 6,052,313, a 1-transistor type memory cell with a floating gate is used for a fuse cell. The 1-transistor type memory cell is a nonvolatile memory cell which varies a threshold value in accordance with whether or not electrons are injected to the floating gate, and “0” or “1” data is stored depending on the change of the threshold value.
In the 1-transistor type memory cell, however, the memory cell must accurately be controlled whether to turn on or off. This is to prevent data error. Consequently, at the time of writing data, the threshold value must be strictly adjusted, and it takes time to write data.
In addition, the 1-transistor type memory cell requires a large current, for example, to inject electrons into the floating gate by the use of hot-electron when data is written. Therefore, current consumption is also large.